2023年12月11日 星期一

SystemVerilog DPI 介紹 (1)

什麼是 DPI?

自 SystemVerilog3.1a之後,SystemVerilog 推出了一個與第三方語言介接的功能,稱之為DPI(Direct Programming Interface),可以方便在SystemVerilog中引入其它的語言來使用。在本文中將介紹其中最常被使用的 C語言,說明如何在 SystemVerilog中運行以 C語言所寫成的功能。


基本用法

在 SystemVerilog 使用 import 來呼叫 C function。
import 的語法:

import "DPI" [from_c_name =] [pure][context] function type to_sv_name(args);
import "DPI" [from_c_name =] [context] task to_sv_ame (args);


lab1.sv
module top;
    import "DPI-C" context function void helloDPI();
    initial begin
        helloDPI();
    end
endmodule

helloDPI.c
#include <stdio.h>
void helloDPI()
{
    printf("-----------\n");
    printf(" Hello DPI\n");
    printf("-----------\n");
}

run.do
vlib work

# Compile the HDL source(s)
vlog -sv -dpiheader dpiheader.h lab1.sv helloDPI.c

# Simulate the design.
onerror {quit -sim}
vsim -c top
run -all
quit -f

編譯指令

vsim -c -do run.do

運行結果





2021年9月28日 星期二

Testbench

  initial 

begin

$dumpfile("root_tb.vcd");


`ifdef POST_SIM

$dumpvars( 1, uut );

`else

/*

$dumpvars ( 

2, 

uut.I_image_process_A, 

uut.I_cis2_a_ctrl.I_image_edge_fifo

);

*/

$dumpvars;

`endif


end


`ifdef POST_SIM


initial 

begin


// 

// sdf_annotate example:

//

// $sdf_annotate ("<design_name>.sdf", <instance_name>, ,<sdf_log>, "MAXIMUM");

//

$sdf_annotate ("../Implementation/Canon/ecp3_trial/ecp3_trial_vo.sdf", uut );

end


`endif

2021年6月6日 星期日

chk_rtl_file.sh

 #!/bin/sh

# Updated date : 2020/02/20

# Set default golden_path and reverse_path

Impl_path="../../Implementation"

impl_level=6

#Impl_path="../../../../../AM-12M/FPGA/Implementation"

#impl_level=11

# Choose implementation directory manually.

echo "==========================================="

echo "Please choose FPGA implementation : "

echo "==========================================="

ls -F ../../ | grep "Impl" | sed 's/\///' | \

awk 'BEGIN { num = 0 } 

   { print num "-" $1 ;

print num "-" $1 > "list.data" ; 

num +=1 }'

read project_num

Impl_dir=`cat list.data | grep -w "^$project_num" | cut -d '-' -f 2`

echo "Check implementation directory is $Impl_dir"  

Impl_path="../../$Impl_dir"

# Choose FPGA design.

echo "==========================================="

echo "Please choose FPGA version : "

echo "==========================================="

ls -F $Impl_path | grep "/" | sed 's/\///' | \

awk 'BEGIN { num = 0 } 

   { print num "-" $1 ;

print num "-" $1 > "list.data" ; 

num +=1 }'


read project_num

project_file=`cat list.data | grep -w "^$project_num" | cut -d '-' -f 2`

echo "Check project file is $project_file"  

golden_path="."

reverse_path="$Impl_path/$project_file/source"

# Back up old file

echo ""

if [ -f diff_rtl.log ]; then

echo "Move diff_rtl.log to x_diff_rtl.log"

cp diff_rtl.log x_diff_rtl.log

rm diff_rtl.log

fi

# Print basic infomation

echo ""

echo "Check RTL Files" | tee -a diff_rtl.log

echo "" | tee -a diff_rtl.log

echo "golden_path  = $golden_path"  | tee -a diff_rtl.log

echo "reverse_path = $reverse_path " | tee -a diff_rtl.log

echo "" | tee -a diff_rtl.log

# Generate file list

#

find ../ -name "*.v" | sort > golden_file.log

#find $reverse_path -name "*.v" | sort | grep -v '/IP/\|/Testbench/' > reverse_file.log

find $reverse_path -name "*.v" | grep -v "_tmpl\." | sort | grep -v '/Testbench/' > reverse_file.log

# cat golden_file.log | rev | cut -d "/" -f 1 | rev

# Execute Diff

#for i in `cat golden_file.log | rev | cut -d "/" -f 1-2 | rev | sed 's/^/\//'`

#for i in `cat golden_file.log | sed 's/^.//'`

start=`date +%s`

for i in `cat reverse_file.log | cut -d "/" -f $impl_level- | sed 's/^/\//'`

do

echo "===== START `cat reverse_file.log | grep $i` =====" >> diff_rtl.log

#echo "===== grep $i =====" >> diff_rtl.log

diff -w `cat reverse_file.log | grep $i` `cat golden_file.log | grep $i` >> diff_rtl.log

done

end=`date +%s`

runtime=$((end-start))

echo "----"

echo "runtime is $runtime."

echo "----"

echo "-------------------------------------" >> diff_rtl.log

echo " DIFF golden_file & reverse_file     " >> diff_rtl.log

echo "-------------------------------------" >> diff_rtl.log

#cat reverse_file.log |\

#    cut -d "/" -f 6- |\

#    sed 's/^Design\//.\//' |\

sed 's/^Design_definition\//..\/&/' > reverse_file2.log

cat reverse_file.log | cut -d "/" -f 6- | sed 's/^/\//' > reverse_file2.log

#cat golden_file.log | grep -v '/IP/\|/Testbench/' | sort | sed 's/^\.\.//' > golden_file2.log

cat golden_file.log | grep -v '/Testbench/' | sort | sed 's/^\.\.//' > golden_file2.log

diff golden_file2.log reverse_file2.log >> diff_rtl.log

echo -- >> diff_rtl.log

date >> diff_rtl.log

echo -- >> diff_rtl.log


echo ""

echo "Different files are -->"

echo ""

cat diff_rtl.log | grep -B 1 -v '=====\|-----' | grep "====="

echo ""


echo DONE


rm golden_file.log

rm golden_file2.log

rm reverse_file.log

rm reverse_file2.log

rm list.data


2021年5月18日 星期二

測試手法

關於測試的部分:

測試項目分成四大項(單筆、多筆、壓力、ThroughPut),

量測的時間點分成三段(Waiting、Transfer、Ending)、

2021年4月25日 星期日

Verilog 連結暫存

 這裡暫記一些與 Verilog 有關的連結:


Verilog Behavioral modeling 


https://technobyte.org/behavioral-modeling-verilog/

Makefile 範例

all: work rtl agents uvm_tb tb sim_all


work:

vlib work


rtl:

vlog ../rtl/uart/*.sv +cover=sbf


agents:

vlog ../agents/apb_agent/apb_if.sv

vlog +incdir+../agents/apb_agent ../agents/apb_agent/apb_agent_pkg.sv

vlog ../agents/uart_agent/serial_if.sv

vlog +incdir+../agents/uart_agent ../agents/uart_agent/uart_agent_pkg.sv

vlog ../agents/modem_agent/modem_if.sv

vlog +incdir+../agents/modem_agent ../agents/modem_agent/modem_agent_pkg.sv


uvm_tb:

vlog ../uvm_tb/register_model/uart_reg_pkg.sv

vlog +incdir+../uvm_tb/env ../uvm_tb/env/uart_env_pkg.sv

vlog +incdir+../uvm_tb/sequences ../uvm_tb/sequences/host_if_seq_pkg.sv

vlog +incdir+../uvm_tb/sequences ../uvm_tb/sequences/uart_seq_pkg.sv

vlog +incdir+../uvm_tb/virtual_sequences ../uvm_tb/virtual_sequences/uart_vseq_pkg.sv

vlog +incdir+../uvm_tb/tests ../uvm_tb/tests/uart_test_pkg.sv


tb:

vlog ../uvm_tb/tb/interrupt_if.sv

vlog ../protocol_monitor/apb_monitor.sv

vlog ../uvm_tb/tb/uart_tb.sv

sim_all: sim_word_format_poll sim_modem_poll sim_word_format_int sim_modem_int sim_baud_rate sim_uart_regs


sim_word_format_poll:

vsim uart_tb +UVM_TESTNAME=word_format_poll_test -do "coverage save word_format_poll.ucdb -onexit;run -all" -c -l word_format_poll.log -coverage -voptargs=+acc


sim_modem_poll:

vsim uart_tb +UVM_TESTNAME=modem_poll_test -do "coverage save modem_poll.ucdb -onexit;run -all" -l modem_poll.log -c -coverage


sim_word_format_int:

vsim uart_tb +UVM_TESTNAME=word_format_int_test -do "coverage save word_format_int.ucdb -onexit;run -all" -l word_format_int.log -c -coverage


sim_modem_int:

vsim uart_tb +UVM_TESTNAME=modem_int_test -do "coverage save modem_int.ucdb -onexit;run -all" -l modem_int.log -c -coverage


sim_baud_rate:

vsim uart_tb +UVM_TESTNAME=baud_rate_test -do "coverage save baud_rate.ucdb -onexit;run -all" -l baud_rate.log -c -coverage


sim_rx_errors_int:

vsim uart_tb +UVM_TESTNAME=rx_errors_int_test -do "coverage save rx_errors_int.ucdb -onexit;run -all" -l rx_errors_int.log  -voptargs=+acc


sim_uart_regs:

vsim uart_tb +UVM_TESTNAME=uart_test -do "coverage save uart_regs.ucdb -onexit;run -all" -l uart_regs.log -c -voptargs=+acc


# vsim uart_tb +UVM_TESTNAME=rx_errors_int_test -do "coverage save rx_errors_int.ucdb -onexit;run -all" -l rx_errors_int.log -c -coverage



clean: 

rm -r work

rm *.log transcript vsim.* *.ucdb 


tarball: clean tgz


tgz:

@(cd ../..; \

tar -zcf uart_example/sim/uart_example.tgz \

uart_example/agents \

uart_example/docs \

uart_example/protocol_monitor \

uart_example/rtl \

uart_example/uvm_tb \

uart_example/README \

uart_example/sim/Makefile)


SystemVerilog DPI 介紹 (1)

什麼是 DPI? 自 SystemVerilog3.1a之後,SystemVerilog 推出了一個與第三方語言介接的功能,稱之為DPI(Direct Programming Interface),可以方便在SystemVerilog中引入其它的語言來使用。在本文中將介紹其中最常...